1. Field of the Invention
The present invention relates to a semiconductor memory device such as a mask ROM (read only memory), and more particularly relates to a circuit technique which achieves increase in size and reduction in power consumption for memory cell arrays.
2. Description of the Prior Art
As a read only memory, for example, a contact-type mask ROM has been known. A contact-type mask ROM is a semiconductor memory device which stores data of “0” or “1” according to whether or not a drain of a memory cell transistor constituting a memory cell is connected to a bit line.
In the contact-type mask ROM, the number of memory cells per bit line is increased, thereby realizing increase in the size of a memory cell array. Therefore, suppression of a current steadily generated by an OFF leakage current of a memory cell has been required.
A semiconductor memory device 900 is an example of a contact mask ROM formed so as to have a configuration in which an OFF leakage current is reduced. The semiconductor memory device 900 is so configured that in reading data, a potential difference between a source and a drain in a non-selected memory cell is reduced by making a potential of a source line which is not connected to a memory cell from which data is to be read out be the same potential as a precharge potential of a bit line to reduce an OFF leakage current (see, for example, Japanese Laid-Open Publication No. 2003-31749).
FIG. 10 is a block diagram illustrating a configuration of the semiconductor memory device 900. As shown in FIG. 10, the semiconductor memory device 900 includes a plurality of memory cell arrays 910, a source potential control circuit 920, a plurality of column decoders 930, a plurality of precharge transistors 940, a plurality of read out circuits 950 and an output selection circuit 960.
Each of the memory cell arrays 910 includes a plurality of memory cells 911 in a matrix of n rows and m columns. In each of the memory cell arrays 910, word lines (WL0 through WLn−1) and source lines (SN0 through SNn−1) are provided so as to correspond to the rows of the matrix, respectively. Also, in each of the memory cell arrays 910, bit lines (BL00 through BL1m−1) are provided so as to correspond to the columns, respectively.
Each of the memory cells 911 is specifically formed of a transistor. A gate of each of the memory cells (transistors) 911 is connected to one of the word lines corresponding to one of the rows to which one of the memory cells 911 belongs. A source node of each of the memory cells 911 is connected to one of the source lines corresponding to one of the columns to which one of the memory cells 911 belongs. Each of the memory cells 911 stores data of “0” or “1” according to whether or not a drain is connected to one of the bit lines corresponding to one of the columns to which one of the memory cells 911 belongs.
The source potential control circuit 920 includes a plurality of NOT circuits 921 provided so as to correspond to the word lines, respectively. Each of the NOT circuits 921 supplies a signal, obtained by inversion of a level of an associated one of the word lines, to an associated one of the source lines. For example, a signal obtained by inversion of a word line WL0 is supplied to a source line SN0.
Each of the column decoders 930 includes a plurality of switches provided so as to correspond to the bit lines, respectively. The switches receive column selection signals CA0 through CAm−1 indicating which bit line to be selected, respectively. One of the switches connects one of the bit lines which is to be selected to an associated one of the precharge transistors 940 and an associated one of the read out circuits 950.
Each of the precharge transistors 940 precharges an associated one of the bit lines connected to the precharge transistor 940 via an associated one of the column decoders 930 according to a precharge signal (PCLK0 or PCLK1).
Each of the read out circuits 950 reads data output to an associated one of the bit lines connected thereto via an associated one of the column decoders 930 and outputs the data to the output selection circuit 960.
The output selection circuit 960 selects one of two data (SOUT1 and SOUT2) read out by two of the read out circuits 950 according to a selection signal SEL and outputs the selected data.
The operation of the semiconductor memory device 900 formed so as to have the above-described configuration when data is read out from one of the memory cells connected to the word line WL0 will be described with reference to a timing chart shown in FIG. 28.
When the semiconductor memory device 900 is in a stand-by state before a time A, in the semiconductor memory device 900, each of the word lines is the Low (L) level, so that the source lines are all kept at the High (H) level.
For example, when the column selection signal CAm−1 is deactivated in response to a read out request received from the outside at the time A, one of the switches which has received the column selection signal CA0 is turned ON. Thus, a bit line BL00 is connected to an associated one of the precharge transistors 940 and an associated one of read out circuits 950. Next, when the precharge signal PCLK0 is activated and then one of the precharge transistors 940 is turned ON, only the bit line BL00 is precharged to be the H level.
When the selected word line WL0 is activated, a source line SN0 is pulled down to the L level. In this case, the other ones of the source lines than the source line SN0 stay at the H level. In one of the memory cells activated by the word line WL0, when a drain is connected to the bit line BL00, the bit line BL00 is pulled down to the L level. If the drain is not connected to the bit line BL00, the bit line BL00 is kept to be in a state where the bit line BL00 is precharged to the H level.
Next, data (signal) of the bit line BL00 is read out by an associated one of the read out circuits 950. An output signal SOUT0 of the read out circuit 950 is latched at a rise timing of the selection signal SEL and is output as an output DOUT to the outside of the semiconductor memory device 900.
Thereafter, when the word line WL0 returns to the L level, a source node of one of the memory cells 911 connected to the word line WL0 becomes the H level.
As has been described, in the semiconductor memory device 900, when a read out request is received, only one of the source lines connected to selected one of the memory cells is pulled down to the L level, so that an OFF leakage current can be suppressed due to a reverse bias effect in the other ones of the memory cells which are not selected. The OFF leakage current suppression is useful for achieving increase in size of memory cells.
However, in the above-described configuration, since the source lines and the word lines are provided in the one-to-one correspondence, a problem arises in which as a memory capacity is increased, a layout area is increased because of the arrangement of the source lines.
Moreover, when the semiconductor memory device 900 is in a stand-by state, all of respective source nodes of memory cells are kept to be in the H level. Thus, as a memory capacity is increased, while reduction in size is achieved, an OFF leakage current in a memory cell is increased. Accordingly, in the semiconductor memory device as a whole, power consumption tends to be increased.
To suppress an OFF leakage current, a voltage of each source node is preferably 0.1 through 0.2 V (specifically, in the 65 nm process, if a source node voltage is increased by 0.1 V, an OFF leakage current can be suppressed so as to be two orders in magnitude smaller). However, in the known configuration, the source node voltage is increased to the VDD level or the VDD-Vtn (Vtn is a threshold potential of an n-channel transistor constituting a memory cell). That is, there has been a problem in which more power than necessary for suppressing an OFF leakage current is consumed.